The present invention relates generally to integrated circuit design tools and, in particular, to noise optimization in an integrated circuit.
Signal integrity (SI) is a critical issue for Deep Sub Micron (DSM) Integrated Circuits (ICs). Devices in an IC are connected through interconnects. However, as ICs are scaled down in size, there is a corresponding increase in interconnect density, which can introduce unwanted components of capacitance, resistance and inductance in one or more nets of an IC. These unwanted components result in crosstalk noise, which includes functional noise and delay noise. The nets on which crosstalk noise is injected by one or more neighboring nets are called victim nets and the nets that inject the noise are called aggressor nets. Functional noise occurs when a victim net does not switch at the time of switching of the aggressor nets. However, when the victim net also switches at the time of switching of the aggressor nets, the victim net's delay can either increase or decrease depending on the aggressor nets' and the victim's switching directions, which results in delay noise that can cause setup or hold time failures. Therefore, delay noise needs to be minimized to achieve targeted performance metrics.
In conventional methods for reducing delay noise, a static timing analysis is carried out in an IC design flow after routing and extraction have been performed. The static timing analysis provides violations caused by the delay noise. These violations are then fixed by repeating the previous design flow steps such as routing or placement of devices. The process is repeated until all the violations are fixed, which increases the design time considerably. Further, the method depends on complex and unpredictable repair flows. Also, it does not prevent the occurrence of delay noise and is not cost-effective.
Accordingly, it is an object of the present invention to provide a method and system for reducing delay noise in an IC.